1. Field of the Invention
The invention relates to a method of manufacturing an integrated semiconductor substrate structure provided with a first device area for definition of GaN-based devices and a second device area for definition of CMOS devices.
The invention also relates to an integrated semiconductor substrate structure thus formed.
The invention further relates to a method of manufacturing an integrated circuit with the integrated semiconductor substrate structure.
2. Description of the Related Technology
GaN is a promising candidate for use for power applications as well as for optical applications. Examples hereof include the manufacture of light emitting diodes, power amplifiers, power converters. In order to control this type of devices, control electronics is typically needed. In order to exploit the high quality of the GaN devices and to meet the demand for functionality and for small size, integration of control electronics and the GaN devices is considered beneficial. Such integration is moreover in line with advanced developments to use a silicon substrate for the growth of a GaN heterostructure. Several substrates and several crystal orientations of the substrate have been used. Particularly, a silicon substrate with a (111) orientation has been found an interesting candidate. A major challenge in the growth of GaN on Si(111) has been the large mismatch of the in-plane thermal expansion coefficient (5.59×10-6 K−1 for GaN and 2.6×10-6 K−1 for Si). This tends to lead to cracking in the GaN layer when cooling the heterostructure from the growth temperature to room temperature. This problem has been considerably reduced by using a low temperature AlN buffer layer or interlayer.
Recently, it has been found out that the use of a silicon-on-insulator (SOI) substrate leads to beneficial results. Experiments with both a (001) orientation and a (111) orientation of the device layer have been carried out. Zhou, Applied Physics Letters 86 (2005), 081912, reported the growth of GaN on a device layer of the SOI substrate structure with a (111) orientation. The SOI substrates were commercially prepared by SIMOX (separation by implanted oxygen) technology. The thickness of the silicon device layer and the buried dielectric layer of SiO2 were 200 nm and 360 nm, respectively. The GaN layers were grown directly on this SOI substrate without any buffer layer in a MOCVD reactor using H2 as the carrier gas. Prior to GaN deposition, the substrates were heated to 1100 C for 10 minutes under H2 ambient to remove the native oxide from the substrate surface. Subsequently, the GaN layer was deposited at 1100 C. The crystalline quality of the GaN layer appears to be directly influenced by the Si device layer.
US20060284247 discloses the integration of AlGaN/GaN amplifiers with silicon CMOS circuits. A planarization layer of amorphous or polycrystalline silicon and a thin layer of single crystalline silicon were formed on a SiC substrate Thereafter, a GaN heterostructure comprising AlGaN and GaN layers was grown epitaxially. A protection layer of silicon nitride or silicon oxide was deposited on the GaN heterostructure. Following this, a silicon layer is bonded to the protection layer particularly in the form of an SOI substrate with its top layer bonded to the passivation layer. The SOI substrate is thereafter thinned so as to remove its handling wafer and its buried oxide. The resulting silicon device layer typically has a thickness of 50 to 200 nm. A first device area for the definition of GaN devices was defined, and the silicon is etched away in those areas. Following this, CMOS devices are fabricated on the silicon layer in a second device area, and GaN devices are fabricated on the GaN hetero structure.
It is a disadvantage of the known method that the bonding process is still delicate, and may not result in a strong bond. The known method preferably applies grooves into one or more of the layers at the bonding interface so as to remove residual gases from the interface. These grooves are particularly needed at the center of the wafer, where otherwise the bond would not be good enough. The grooves are typically at a pitch between 1 and 2 mm. This however implies that the pitches will be present within the final chip, and thus that the amount of available surface area decreases.
Furthermore, there is still a need for an annealing process to complete the bonding process. This annealing process was 175 degrees Celsius for a 4 inch wafer and it took 24-100 hours. Higher temperatures could be used, up to 1150 degrees Celsius, Moreover, such high temperatures are also needed for the definition of CMOS devices after completion of the substrate structure. The high temperature gives rise to temperature differences during cooling, leading to thermal stress. This thermal stress becomes more dramatic with increase in substrate size. The 4 inch substrate used in the prior art is not anymore representative of industrial processing of CMOS, which uses substrate sizes of 8 inch and 12 inch diameter. Diffusion of silicon into the GaN would be another result of such high temperature process. The silicon typically diffuses from silicon oxide that is typically used as bonding layer. Such diffusion of silicon tend to deteriorate the material properties of the GaN layers, and therewith also device properties such as mobility
In short, the known method and device has several drawbacks and is not industrially viable.
It is therefore desirable to provide an improved device which is less sensitive to diffusion of silicon and/or oxide particles into the GaN layers.
It is also desirable to provide an improved method for the manufacture of an integrated semiconductor substrate structure on which GaN devices can be defined in a first device area and on which CMOS circuits can be defined in a second area.
It is also desirable to provide an improved method of manufacturing of a integrated circuit with both GaN and CMOS devices and to provide improved devices.